1. Field of the Invention
The present invention relates to a semiconductor device wherein dummy patterns are formed on a semiconductor substrate together with a wiring pattern, and to a method of manufacturing the semiconductor device.
2. Description of the Related Art
In an interlayer film CMP (Chemical mechanical polishing) process, batch polishing has heretofore been performed to reach an intended or target remaining film thickness set value. When, at this time, a polishing pad which is brought into contact with the surface of a wafer is elastically deformed due to pressure from an underlying step at an initial polishing stage, the pressure that is applied from the polishing pad increases when a pattern density is low, whereas the pressure that is applied from the polishing pad is dispersed and becomes low when the pattern density is high, thus causing a difference in the polishing rate between loose and dense wiring pattern portions.
Thus, the remaining film thickness differences (hereinafter might be called “global steps”) occur among the loose and dense wiring pattern portions after polishing. Each of the global steps consists of a difference in film thickness at the loosest portion and the densest portion of the underlying wiring pattern. The global steps are different from one another according to a wiring layout. Therefore, when the global step is large in the interlayer film CMP process, the underlying wiring pattern is exposed or disappears at the loose portion of the underlying wiring pattern, and the residual step occurs due to cutting insufficiency at the dense portion of the underlying wiring pattern.
When such exposure, disappearance and residual steps of the underlying wiring pattern occur, no wiring is formed upon forming each wiring in a subsequent process, thus causing degradation in yield and reliability.
Therefore, dummy patterns (pseudo dummy patterns) which are different from an actual wiring pattern are inserted into the entire surface of a chip to set the global steps as low as possible (refer to, for example, a patent document: Japanese Unexamined Patent Publication No. 2003-140319). The global steps vary depending on whether the dummy patterns exist. The insertion of the dummy patterns provides an improvement in the global step.
However, a disadvantage occurs in that when the dummy patterns are inserted, a pattern ratio (pattern proportion) of a mask becomes too large to carry out an end point detector (EPD) upon etching at the formation of a wiring pattern. Therefore, there is a demand for suppressing the insertion of the dummy patterns as low as practicable to thereby reduce the global steps.
While the dummy patterns may preferably be inserted to improve the global steps in this way, a disadvantage occurs in that when the pattern ratio become excessively large, EPD cannot be detected upon etching of the wiring pattern.